JEDEC STANDARD Board Level Drop Test Method of Components for Handheld Electronic Products JESDB JULY JEDEC SOLID. The reliability of this package has been studied by employing the JEDEC JESDB standard drop test. In this paper, the JEDEC B-condition is applied to. The need for RoHS compliant boards coupled with the demand for reliable electronics has resulted in the development of the JEDEC Standard JESD B to.
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In case of rectangular components, the longer side of the component should be parallel to the longer side of the board when mounted. The primary driver of these failures is excessive flexing of circuit board due to input acceleration to the board created from dropping the handheld electronic product. The high-speed data acquisition system should be able to measure resistance with a sampling rate of 50, samples per second or greater.
Different methods and equipment, such as visual inspection, cross-section, dye and pry, chemical etching, SEM, and SAT can be employed to determine the root cause of failure. The thickness and mounting locations of the base plate shall be selected such there is no relative movement between the drop table and any part of base plate during drop testing.
All components used for this testing must be daisy-chained. Effect of Thermal Agin This is pictorially shown in Figure 3.
BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS
In that case, the components shall be mounted on each side of the board. However, a mix of different component sizes and styles shall not be used on the same board, as this will affect the dynamic response of the board, making the results difficult to analyze. All failures after each drop shall be logged.
This flexing of the board causes relative motion between the board and the components mounted on it, resulting in component, interconnects, or board failures. The test data generated using such a board shall be correlated at least once by generating the same data on same component using the preferred board defined in this document.
Drop testing on other board orientation is not required but may be performed if deemed necessary. The PTH pad diameters shall be microns for the outer layer and microns for the inner layers.
It should be noted that the peak acceleration mesd22 the pulse duration is a function of not only the drop height but also the strike surface. The free-fall drop height of the drop table needed to attain the prescribed peak acceleration and pulse duration. The failure is a strong function of the combination of the board design, construction, material, thickness, and surface finish; interconnect material and standoff height; and component size. All components must be located within the 95 mm X 61 mm box shown by the dashed line jjesd22 Figure 1 defined by the outer edges of all outer components.
If you can provide input, please complete this form and return to: Figure 3 shows the typical drop test apparatus where the drop table travels down on guide rods and strikes the rigid fixture.
This is the applied shock pulse to the base plate and shall be measured by accelerometer mounted at the center of base plate or close to the support posts for the board.
The PCB assembly shall be mounted to the base b1111 standoffs using 4 screws, one at each corner of the board.
BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS | JEDEC
The maximum jesc22 size shall be 15 mm in length or width and there shall be at least 5 and 8 mm gap between the components in x- and y-direction, respectively.
Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. Adjustments in drop height or replacement of jesr22 surface may be needed if the pulse deviates from the specified. The maximum number of drops shall be 30 irrespective of single or double-sided assembly.
The additional data shall directly compare the effect of optional component mounting 1 or 5 components to the preferred component mounting configuration. This shall be accomplished by designing double sided boards with mirror component footprint on each side top and bottom of the board.
There shall be four holes on the board to be used for mounting board on drop test fixture. Publications Department Wilson Blvd. All routing and traces within and just outside the component footprint shall be done on layer 2 and layer 8 for area array packages and layer 1 and layer 8 for perimeter leaded packages.
Other shock conditions, such as Condition H Gs, 0. The initial resistance of all nets for each assembly shall be measured and logged before conducting the first drop. It is recommended to first analyze the component reliability data at individual locations without assuming any grouping.
jesx22 All assemblies shall be single side only unless the component is anticipated for use in mirror-sided board assemblies. This is not a component qualification test and is not meant to replace any system level drop test that maybe needed to qualify a specific handheld electronic product. Component length and width.
The modulus and Tg of the dielectric materials shall be specified. The electrical failures may result from various failure modes such as cracking of circuit board, trace cracking on the board, cracking of solder jjesd22 between the components and the board, and the component cracks.