Home · Documentation; ihi; a – AMBA® 3 AHB-Lite Protocol v Specification. AMBA 3 AHB-Lite Protocol Specification v AMBA AHB-Lite addresses the requirements of highperformance . The AHB- Lite specification differs from AHB specification in the following. to design modules that conform to the AMBA specification. Organization .. The AHB acts as the high-performance system backbone bus.

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It facilitates development of multi-processor designs with large numbers of controllers and peripherals with a bus architecture.

Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller devices.

These protocols are today the de facto standard for embedded processor bus architectures because they are well documented and can be used without royalties. An important aspect of a SoC is not only which components or blocks it houses, but also how they interconnect.


AMBA 3 AHB-Lite Protocol Specification v1.0

AMBA is a solution pite the blocks to interface with each other. The AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers.

spex It is supported by ARM Limited with wide cross-industry participation. The timing aspects and the voltage levels on the bus are not dictated by the specifications.

Advanced Microcontroller Bus Architecture – Wikipedia

AXIthe third generation of AMBA interface defined in the AMBA 3 specification, is targeted at shb performance, high clock frequency system designs and includes features that make it suitable for high speed ahhb interconnect:. A simple transaction on the AHB consists of an address phase and a subsequent data phase without wait states: Access to the target device is controlled through a MUX non-tristatethereby admitting bus-access to one bus-master at a time.

This subset simplifies the design for a bus with a single master. APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals.


This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list for example no bursts. From Wikipedia, the free encyclopedia. Technical and de facto standards for wired computer buses.

Interfaces are listed by their speed in the roughly ascending order, so the interface at the end of each section liet be the fastest.

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